FIG. 1 (prior art) depicts a type of clock distribution network 100 commonly used to source clock signals in complex, high-speed integrated circuits. Network 100 includes a phase-locked loop (PLL) 105, a clock-enable multiplexer 110, and a clock network 115. In operation, PLL 105 generates a stable clock signal CLK from a reference clock signal REF. When clock-enable signal CLKEN is asserted, multiplexer 110 conveys clock signal CLK to network 100 for distribution to a plurality of clock destination nodes CD[0:N].
PLL 105 includes a phase detector 120, a low-pass filter 125, and a voltage-controlled oscillator (VCO) 130. A feedback path extending between the output of VCO 130 and one of two input terminals of phase detector 120 conveys a feedback signal SENSE derived from clock signal CLK. Phase detector 120 compares the phase of feedback signal SENSE with that of reference signal REF and produces a phase-error signal PE based upon this comparison. Low-pass filter 125 then presents a filtered version of the phase-error signal as an input voltage V to VCO 130. The frequency of signal CLK is proportional to voltage V, so phase detector 120 controls clock signal CLK via filter 125 to maintain a fixed phase relationship between signals SENSE and REF.
The feedback path of PLL 105 optionally includes a divider 135, the effect of which is to multiply the frequency of clock signal CLK with respect to reference signal REF. A delay element 140 (e.g., a buffer) included in the feedback path is selected such that the delay through the feedback path is substantially the same as the delay through each clock path extending from VCO 130 to the various destination nodes CD[0:N]. Each clock branch includes one or a series of clock buffers that are collectively represented using a single buffer 145 in each path. Delay element 140 and buffers 145 can be carefully designed such that the delay through the feedback path of PLL 105 matches the delay through the various clock paths. In that case, signal SENSE should have a fixed phase and frequency relationship with respect to the distributed clock signals at destination nodes CD[0:N].
Broadcasting clock signals can consume considerable power, particularly for high-speed systems in which there are many destination nodes. Network 115 therefore employs multiplexer 110 to selectively disable the distribution of clock signal CLK to destination nodes CD[0:N] when the synchronous elements served by the distributed clock signals are inactive. Clock signals to a transmitter may be delivered only when the transmitter is in use, for example. Asserting clock-enable signal CLKEN connects the output of PLL 105 to clock network 115, and thus conveys clock signal CLK to destination nodes CD[0:N]. Deasserting signal CLKEN couples the inputs of buffers 145 to ground.
At start-up, such as when power is first applied to network 100, PLL 105 requires some time to lock feedback signal SENSE to reference signal REF. To avoid undesirable performance delays, PLL 105 maintains the lock condition irrespective of whether clock-enable signal CLKEN is asserted.
The destination clock signals should be synchronized to reference signal REF, which will be the case if the delay through clock network 115 matches the delay through delay element 140. It is therefore important that delay element 140 be carefully designed to replicate the behavior of buffers 145. Such behavior matching can be difficult in practice, however, because process, voltage, and temperature can each vary from one region of an integrated circuit to the next, and each of these variables impacts speed performance.